This invention relates to charge coupled devices, and more particularly to fast-dump gate formed within charge coupled devices.
The charge coupled device (CCD) art is replete with teachings for selectively removing charges in a predetermined manner. Fast-dump gates are typically used within prior art devices in the area of a horizontal CCD (HCCD) shift register to: (1) read out data from the horizontal CCD; or (2) selectively dump lines of data from the horizontal shift register in sub-sampling modes.
A conventional prior art device employing fast-dump gate structure is shown in FIG. 1 with two levels of polysilicon used to form the CCD electrodes. The two levels of polysilicon are indicated as H1 for the first level of polysilicon and H2 for the second level of polysilicon. Boron implants are used to form the two-phase CCD barrier regions in FIG. 1 and are indicated as BR1A for H1 and BR2A for H2. Each of the H1, H2 electrodes has an n-type buried channel beneath the poly1, poly2 electrodes in the prior art device shown in FIG. 1. The problem with these prior art devices is that CCD cell of the horizontal shift register which is to be connected to the fast-dump gate (shown as H1) has an effective width W2 that increases as the H1 cell of the horizontal shift register approaches the FDG along the length L2, yielding a well. Other prior art devices have an effective width W2 that decreases as it approaches the FDG along the length L2 creating a barrier.
FIG. 2a is a cross sectional view of FIG. 1 along the line AA with associated potential diagrams 2b and 2c for cases where the effective channel width decreases as it approaches the fast-dump gate and the effective channel width increases as it approaches the fast-dump gate. The actual width W2 is drawn larger than W1 to compensate for the encroachment of an implanted boron channel stop so that W2eff=W1eff. However, if W2eff greater than W1eff, a well is formed which is illustrated in FIG. 2c, and if W2eff less than W1eff, a barrier is formed which is illustrated in FIG. 2b. The length L2 is a requirement that is dictated and determined by two level polysilicon space design rules to prevent H2 and FDG from shorting together. When W2eff less than W1eff, a barrier exists which inhibits charge flow into FDD during fast-dump operation as shown in FIG. 2b. When W2eff greater than W1eff, no barrier exists in xe2x80x9cL2xe2x80x9d region and fast-dump operation works fine, but when FDG is off, a potential well exists in this region which can trap charge during HCCD readout as shown in FIG. 2c. 
FIG. 2d is a diagram illustrating the narrow width effect that is cured by the present invention. As the width increases, the potential shown as xcfx86 (v) increases and then eventually flattens out.
Referring to FIG. 3, which is a cross sectional view of FIG. 1 along the line BB parallel to and through HCCD showing width W1. The two levels of polysilicon are indicated as poly1 and poly2 for H1 and H2, respectively. The boron implants that form the barrier regions are indicated as BR1A for H1 and BR2A for H2. Each of the H1, H2 electrodes has an n-type buried channel beneath the poly1 poly2 electrodes.
Referring to FIG. 4, which is a cross-sectional view of FIG. 1 through the line CC and parallel to HCCD through the bottom part of H1 showing second width, W2. The boron implants resulting in p+ channel stops are illustrated as the identifying feature for W2. The p+ channel stops and Local Oxidized Silicon (LOCOS) provide channel isolation. FIG. 4 taken in conjunction with FIG. 1, illustrates that the width W2 increases to compensate for the narrowing effect of the boron implants used to create channel stops, resulting in the barriers and wells as previously discussed.
It should be readily apparent from the foregoing discussion that there remains a need within the art for a fast-dump gate structure that does not have the likelihood of creating barriers and wells that exist with currently available devices.
The present invention solves many of the aforementioned problems within the prior art by providing a structure that comprises a fast-dump gate (FDG) and a fast-dump drain (FDD) that is connected to a horizontal readout register of a solid-state image sensor. Selectively, lines of the captured image (in the form of charge in the readout register) may be cleared or dumped into the FDD through the channel region below the FDG. This feature can be used, for example, to subsample the image or to read a frame out more quickly by throwing away selected lines. This structure uses a third layer of polysilicon (or other suitable gate material) to form the fast-dump gate which is in addition to the other two layers of gate material used to form the gates in the horizontal readout register. This allows the channel region under the FDG to form without the use of highly doped channel stop regions thereby eliminating the narrow-channel effect and any potential wells or barriers that may result in transfer inefficiency often times found with other structures.
Accordingly the present invention provides a solution to the problems within the prior art by providing a charge coupled device having a fast-dump gate (FDG) and a fast-dump drain (FDD) comprising: a charge coupled device having a first and a second level of polysilicon layers used to form electrodes on the charge coupled device; a third level polysilicon layer used to formed the fast-dump gate adjacent to at least one of the cells of the charge coupled device; and a drain that forms the fast-dump drain being operatively connected to the fast-dump gate.
The invention advantages of not creating potential wells and barriers within fast-dump gate structures.